Design of Low Power Shift Register Using Implcit and Explicit Type Flip Flop

Flip-flops is critical timing elements in digital circuits which have a large impact on the circuit speed and power consumption. The performance of flip-flop is an important element to determine the efficiency of the whole synchronous circuit . In an attempt to reduce power consumption in flip-flops a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using TSMC CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design. The proposed design features the best power-delay-product performance in both implicit and explicit type flip flops under comparison. Shift registers can be designed using such flip flop. As a result power consumption is reduced compared to conventional methods. Keywords—Flip-flop (FF), low power, pulse-triggered, shift register.